Here's some info that i've found on different forums..
Mem kit is:
ocz4001024eldcper2-k

400MHz DDR
CL 2-2-2-5

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some dram settings recommended/used by a couple different people:
-------------------------

Trrd at 3
Twr at 2
Twtr at 2
Trwt at 3

---------------------------------------------
FSB: 260
LDT/FSB Freq: auto
CPu FSB Ratio: 10x
CPU startup:1.50v
CPU VId control: 1.50v
CPU VID Special: Auto
LDT Voltage: 1.3v
Chipset Voltage: 1.6v
DRAM Voltage: 2.8v

DRAM Frequency: 200
CPC: Enable
TCL: 2.5
TRCD: 3
TRAS: 5
TRP: 3
TRC: 10
TRFC: 16
TRRD: 2
TWR: 3
TWTR: 2
TRWT: 3
TREF: 3072
Odd Divisor Correct: Disable
DRAM Bank Interleave: Enable

DQS Skew Control: Auto
DQS Skew Value: 0
DRAM Drive Strength: 7
DRAM Data Drive Strength: Level 2
Max Async Latency: 8.0 ns
DRAM Rewsponse Time: Normal
Read Preamble: 6.0 ns
Idle Cycle Limit: 256 cycles
Dynamic Counter: Disabled
R/W Queus Bypass: 16x
Bypass Max: 7x
32 Byte Granularity: Disable

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Nf4 UT Sli
4/6/06 Bios
4600X2 Manchester
2@ 512 Kingston HyperX Old BH5


Genie BIOS Settings:

FSB Bus Frequency............................. - 223
LDT/FSB Frequency Ratio....................... - x4.0
CPU/FSB Frequency Ratio....................... - 12.0
DFI SLI FX55 Memtimings as follows.
2X1gig OCZ Platinum 3200 DC defaults of 5-2-3-2


FSB Bus Frequency............................. 200 MHz
LDT/FSB Frequency Ratio....................... 5
CPU/FSB Frequency Ratio....................... Auto
PCI eXpress Frequency......................... 100

CPU Voltage .................................. Auto
LDT Voltage .................................. 1.20v
ChipSet (NF4) Voltage ........................ 1.52V
DRAM Voltage ................................. 2.71V
+0.03 if not 3.2V ............................ N/A

Memclock (DRAM Frequency) .................... 200
1T/2T Timing (Command Per Clock).............. 1T
CAS Latency (Tcl)............................. 2T
RAS# to CAS# delay (Trcd)..................... 3T
Min RAS# active time (Tras)................... 8T
Row precharge time (Trp)...................... 2T
Row Cycle time (Trc).......................... 10T
Row refresh cyc time (Trfc)................... 16T
Row to Row delay (Trrd)....................... 3T
Write recovery time (Twr)..................... 3T
Write to Read delay (Twtr).................... 2T
Read to Write delay (Trwt).................... 3T
Refresh Period (Tref)......................... Auto
DRAM Bank Interleave.......................... Enabled

DQS Skew Control.............................. Auto
DQS Skew Value................................ 0
DRAM Drive Strength........................... Level 8, 9, or 10
DRAM Data Drive Strength...................... Level 1 (Reduce 50%) or 2 (Reduce 30%)
Max Async Latency............................. 8ns
DRAM Response Time............................ Normal
Read Preamble Time............................ 6ns
IdleCycle Limit............................... 64
Dynamic Counter............................... Disable
R/W Queue Bypass.............................. 16x
Bypass Max.................................... 4x
32 Byte Granularity........................... Disable (4 Bursts)

stock settings for stock speeds. FX55



PCI eXpress Frequency......................... - 105Mhz

CPU VID StartUp Value......................... - Startup

CPU VID Control............................... - 1.350v
CPU VID Special Control....................... - 110%
LDT Voltage Control........................... - 1.20v
Chip Set Voltage Control...................... - 1.50v
DRAM Voltage Control.......................... - 3.50v

DRAM Configuration Settings:

DRAM Frequency Set............................ - 200
Command Per Clock (CPC)....................... - Enabled
CAS Latency Control (Tcl)..................... - 02Bus Clocks
RAS# to CAS# delay (Trcd)..................... - 02 Bus Clocks
Min RAS# active time (Tras)................... - 05 Bus Clocks
Row precharge time (Trp)...................... - 02 Bus Clocks
Row Cycle time (Trc).......................... - 07 Bus Clocks
Row refresh cyc time (Trfc)................... - 14 Bus Clocks
Row to Row delay (Trrd)....................... - 02 Bus Clocks
Write recovery time (Twr)..................... - 02 Bus Clocks
Write to Read delay (Twtr).................... - 02 Bus Clocks
Read to Write delay (Trwt).................... - 02 Bus Clocks
Refresh Period (Tref)......................... - 3120 Cycles
Write CAS Latency (Twcl)...................... - Auto
DRAM Bank Interleave.......................... - Disabled

DQS Skew Control.............................. - Increase
DQS Skew Value................................ - 50
DRAM Drive Strength........................... - 8
DRAM Data Drive Strength...................... - 4
Max Async Latency............................. - 6
DRAM Response Time............................ - Normal
Read Preamble Time............................ - 5
IdleCycle Limit............................... - 256
Dynamic Counter............................... - enable
R/W Queue Bypass.............................. - 16 x
Bypass Max.................................... - 07 x
32 Byte Granularity........................... - Disable(4 Bursts)